I am grouping some type of files like: http://ift.tt/1BNSKuN
about 100 sub directories...
CC_FILES_TO_BUILD += $(wildcard $(SRC_DIR)/01-Application/*.c)
ASM_FILES_TO_BUILD += $(wildcard $(PROJECT_ROOT)/01-Sources/07-Target/01-MC9S12G/04-STARTUP/01-CPL_LIB/*.s)
When I dump for example CC_FILES_TO_BUILD per rule, I get nice lists of files names.
I then build new lists out these by normal subst to get the corresponding lists of depend files and obj file.
I then want to use these depend and obj list as targets in rules like:
$(CC_TO_MAK_BUILD_LIST):
# do make depend $@
but make doesn't like it, apparently nothing to be done although the files(obj and deps) are not there. No force or phony could solve it for me. According to: http://ift.tt/1AxQ0O6
Wildcard expansion is performed by make automatically in targets and in prerequisites.
make should expand the lists, like CC_TO_MAK_BUILD_LIST, automatically.
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