I need help about designing RAM 32x8 using RAM 8x8

I have a school assignment about designing RAM 32 x 8. I'm using 4 RAM 8 x 8 and a 2-4 decoder which will enable every RAM of 8 x 8 individually. Input[7..0] port: data will be loaded in 8 bit. CS: 'chip select' enable to write or read when CS = 1. A[4..0]: 5 bit address, The 2-bit address will be input as a 2 x 4 decoder, this decoder will have 4 output and the input will have 2 bits. Other 3-bit address will select any word from the 32 words of that RAM, the selected word will be the output as the 8-bit word in the output bus. RWS: Read when RWS = 0, Write when RWS = 1. This is my RTL (package FPGA in quartus): enter image description here But when I simulated in quartus, words in address 0, 8, 16, 24 were false. At first, word writing in A = 0 was 63 and in A = 8 was 29.enter image description here But when it was in Read mod after that (RWS = 0), word in A = 0 was 75 and in A = 8 was 58. Words in A = 16, 24 were false too. But all other address were true.enter image description here

Could you please help me ? Show me whether I was wrong.