Flow through interface in SysML

I was wondering how it would be possible to relate, within a SySML block diagram, the data flowing through two components with the interfaces that they expose.

As an example, assume that you have a supervisor component setting a reference for a lower level controller. The controller exposes an interface Operations which features the operation set_reference() and this latter specifies a float parameter reference. The supervisor will use the interface to effectively set the reference for the lower level controller. This operation tells that there exists a data flow between the two components (e.g. each component also has a flow port) and the exchanged data is the reference. How would you model this scenario in SySML? Does it exist a way to specify both the interface and the dataflow and say "look, this dataflow is realised through this interface".

Thanks a lot for your help