Verilog Sequential Logic: Pattern Recognizer: name-recog.v

Directions for Verilog program: The goal of this assignment is for you to learn to program a Verilog module which recognizes the first five letters of your full name when entered (in the correct order) and indicates by showing a "match" (to be one). Otherwise, it will show the match to be zero.

• The first 5 letters of your full name (composed by your given name, a space, and your family name), character by character case sensitive (only the first letter of your given and family names are upper case).

• A bit-wise ripple memory module can be used to "memorize" a sequence of single bits (as a unary pattern), but not multiple bits in a character. However, if each bit position in a character is to be memorized by one ripple memory module, and with seven memory modules for each of the seven bits in each character; a sequence of characters can thus be memorized.

• As each memory module holds a unary pattern composed by the arrivals of bits from the same bit position in a character, and if the unary pattern matches the bit sequence (from the same bit location); it may declare a match. And when all memory modules collectively indicate so, the character string has been recognized.

Bit Sequence Recognizer

I took the baseline code that was given that recognizes '123' and began to change it to accept a name. I understand the the RecognizerMod is where most of the changes need to be made, but do not understand this part of it:

RippleMod Ripple6(clk, ascii[6], Q[6]);
...

nor(submatch[6], Q[6][2], Q[6][1], Q[6][0]);
...
not(invQ12, Q[1][2]);
and(submatch[1], invQ12, Q[1][1], Q[1][0]);
...

and(match, submatch[6], ... submatch[0]);

Below is the code I have so far.

module TestMod;
  parameter STDIN = 32'h8000_0000; // keyboard-input file-handle address

  reg clk;
  reg [6:0] str [1:6];  // to what's to be entered
  wire match;           // to be set 1 when matched
  reg [6:0] ascii;      // each input letter is an ASCII bitmap

  RecognizerMod my_recognizer(clk, ascii, match);

  initial begin
    $display("Enter the first 5 digits of your name: ");
    str[1] = $fgetc(STDIN);  // 1st letter
    str[2] = $fgetc(STDIN);  // 2nd letter
    str[3] = $fgetc(STDIN);  // 3rd letter
    str[4] = $fgetc(STDIN);  // 4th letter
str[5] = $fgetc(STDIN);  // 5th letter
str[6] = $fgetc(STDIN);  // ENTER key

    $display("Time clk    ascii       match");
    $monitor("%4d   %b    %c %b   %b", $time, clk, ascii, ascii, match);

    clk = 0;

    ascii = str[1];
    #1 clk = 1; #1 clk = 0;

    ascii = str[2];
    #1 clk = 1; #1 clk = 0;

    ascii = str[3];
    #1 clk = 1; #1 clk = 0;

ascii = str[4];
    #1 clk = 1; #1 clk = 0;

ascii = str[5];
    #1 clk = 1; #1 clk = 0;
  end
endmodule

module RecognizerMod(clk, ascii, match);
  input clk;
  input [6:0] ascii;
  output match;

  wire [0:2] Q [6:0];   // 3-input sequence, 7 bits each
  wire [6:0] submatch;  // all bits matched (7 3-bit sequences)

  wire invQ12, invQ01;

  //         654 3210   Q
  //     hex binary
  // '1' 31  011 0001 < q2
  // '2' 32  011 0010 < q1
  // '3' 33  011 0011 < q0

  RippleMod Ripple6(clk, ascii[6], Q[6]);
  ...

  nor(submatch[6], Q[6][2], Q[6][1], Q[6][0]);
  ...
  not(invQ12, Q[1][2]);
  and(submatch[1], invQ12, Q[1][1], Q[1][0]);
  ...

  and(match, submatch[6], ... submatch[0]);

//always @(clk) $display("is %b %b %b %b %b %b %b %b %b",
//   match, submatch, Q[6], Q[5], Q[4], Q[3], Q[2], Q[1], Q[0]);

endmodule

module RippleMod(clk, ascii_bit, q);
  input clk, ascii_bit;
  output [0:2] q;

  reg [0:2] q;          // flipflops

  always @(posedge clk) begin
     q[0] <= ascii_bit;
     q[1] <= q[0];
     q[2] <= q[1];
  end

  initial q = 3'bxxx;
endmodule